A fundamental design challenge in creating a memory cell of an electrically erasable programmable read only memory (EEPROM) device is to use a controllable and reproducible electrical effect that has sufficient non-linearity so that the memory cell (1) can be written to (or erased) at one voltage in less than one millisecond (1 ms) and can be read at another voltage, and (2) the data within the memory cell must remain unchanged for more than ten (10) years.
Prior art stacked/split gate EEPROM technology requires (1) special multi-polysilicon materials, (2) different gate oxide thicknesses, and (3) modified doping profiles. These prior art requirements create process complexity and high cost when embedded into a complementary metal oxide semiconductor (CMOS) process.
In the manufacture of CMOS compatible EEPROM devices it is desirable to maximize the retention reliability of the memory cells. The program and erase operation in a typical memory cell is performed through a “front end” dielectric layer that is located between the floating gate and the silicon substrate of the memory cell. The dielectric layers that are located above the floating gate are referred to as a “backend” dielectric layers. The backend dielectric layers are known to be “leaky” because some of the electrons that are stored on the floating gate will pass from the floating gate through the backend dielectric layers and ultimately move down to the substrate.
This loss of electrons from the floating gate is a unique retention failure mechanism for CMOS compatible nonvolatile memory (NVM) cells. This loss of electrons decreases the retention reliability of memory cells in EEPROM devices.
Therefore, there is a need in the art for a system and method that is capable of solving the problem described above that is exhibited by prior art memory cells. In particular, there is a need in the art for a system and method that provides EEPROM devices that have an improved retention reliability for the electrons that are stored on the floating gates of the EEPROM memory cells.
As will be later described in more detail, the present invention provides a system and method that improves the retention reliability for electrons that are stored on the floating gates of CMOS compatible EEPROM memory cells by using a technique that is known as optical proximity correction. In order to better understand the principles of operation of the present invention, the basic principle of optical proximity correction will first be described.
Optical proximity correction (OPC) is a technique that corrects distortions that occur in a final printed image relative to an original mask design. Optical distortions relative to the original mask design may be introduced by the exposure tool and various processing effects. For example, FIG. 1A illustrates an original mask design 100 that has a rectangular shape. Processing distortions that occur during the mask process may cause the final printed image 110 (as shown in FIG. 1B) to have rounded corners and thus have an oblong shape. Depending upon the type and nature of the distortions, such distortions can lead to a variety of problems such as poor device performance, reliability problems or device failure.
The technique of optical proximity correction attempts to minimize the distortions that are present in the final printed image by altering the shape of the original mask design so that when the distortions occur the final printed image possesses the desired pattern shape. The altered shape of the original mask design compensates for and negates the effect of the distortions.
For example, the original mask design 200 shown in FIG. 2A comprises a rectangular shape that has a square extension 210 located at each corner. The extensions 210 are sometimes referred to as serifs 210. The processing distortions that occur during the mask process cause the final printed image 220 (as shown in FIG. 2B) to have the desired rectangular shape. The extensions 210 in the original mask design 200 have compensated for the effects of the processing distortions.
Optical proximity correction (OPC) has been employed in nonvolatile memory (NVM) layout design to improve design performance. For example, in split gate flash technologies, the corners of the floating gate need to be sharp in order to enhance the Fowler-Nordheim (FN) tunneling current during erase operations. However, it is known that the processing distortions cause the corners of the floating gate to be rounded to some extent. Optical proximity correction (OPC) is used to make compensating adjustments to the shape of the original mask design for the floating gate.
For example, the shape of the original mask design 300 for the floating gate (as shown in FIG. 3A) has been altered to provide extensions 310 on each corner of the floating gate mask. The processing distortions that occur during the mask process cause the final printed image 320 of the floating gate (as shown in FIG. 3B) to have the desired rectangular shape and to have sharp corners 330. The extensions 310 in the original mask design 300 have compensated for the effects of the processing distortions.
For split gate nonvolatile memory (NVM) cells or stacked gate nonvolatile memory (NVM) cells, the Fowler-Nordheim (FN) tunneling erase operation is between the floating gate (FG) and the control gate (CG). A cross sectional view of a typical prior art split gate nonvolatile memory (NVM) cell 400 is shown in FIG. 4. The floating gate is formed from a first polysilicon layer (Poly 1) and the control gate is formed from a second polysilicon layer (Poly 2). The interpoly oxide between the floating gate and the control gate (not shown in FIG. 4) provides the necessary isolation to enable the electrons to remain on the floating gate for up to the required ten (10) year data retention period. A sharp corner on the floating gate enhances the Fowler-Nordheim (FN) tunneling current and facilitates the erase process.
A different situation exists in the case of a CMOS compatible nonvolatile memory (NVM) cell. A cross sectional view of a typical prior art CMOS compatible nonvolatile memory (NVM) cell 500 is shown in FIG. 5. The program operation and the erase operation occur through the “front end” gate oxide that is located between the polysilicon floating gate and the silicon substrate. The leaky “backend” dielectric layers are located over the polysilicon floating gate.
Memory cell 500 comprises a polysilicon gate 510 (designated “POLY GATE 510” in FIG. 5). Polysilicon gate 510 and other elements of the memory cell 500 are covered with backend dielectric 520. In this example backend dielectric 520 is made of tetraethyloxysilane (TEOS). Therefore, backend dielectric 520 is designated as “TEOS 520” in FIG. 5.
Backend dielectric TEOS 520 is covered with backend dielectric 530. In this example backend dielectric 530 is made of silicon oxynitride (SiON). Therefore, backend dielectric 530 is designated “SiON 530” in FIG. 5. Lastly, backend dielectric 530 is covered with backend dielectric 540. In this example backend dielectric 540 is made of plasma enhanced chemical vapor deposition (PECVD) oxide. Therefore, backend dielectric 540 is designated “PECVC oxide 540” in FIG. 5.
The fabrication process for a single poly NVM device is compatible with CMOS devices. The polysilicon gate in an NVM device is a floating gate (FG) that store electrons. The backend dielectric layers (TEOS 520, SiON 530, PECVD oxide 540) have a higher density of defects/traps than a front end gate oxide layer. The higher density of defects/traps enhances the Trap-Assisted-Tunneling (TAT) of electrons in the oxide layers. The higher density of defects/traps enhances thermal excitation in the silicon oxynitride (SiON) layer.
In a CMOS process the silicon oxynitride (SiON) layer is designed to be leaky (i.e., to have more defects/traps) in order to prevent plasma induced damage. Electrons stored on the polysilicon floating gate 510 may tunnel through the TEOS layer 520 to arrive at the leaky silicon oxynitride layer 530 (SiON 530). From the SiON layer 530 the electrons can easily move to the substrate layer (not shown in FIG. 5). This results in a higher charge decay rate for electrons that are stored on the floating gate. This also results in retention degradation especially at higher temperatures.
The phenomenon of backend charge leakage is a serious problem for CMOS compatible NVM devices. Several different methods have been explored to reduce the leakage of charge from the backend dielectric layers in order to improve CMOS compatible retention performance.
A first approach has been to add a mask to the silicon oxynitride (SiON) layer 530 to etch the silicon oxynitride (SiON) layer 530 away from the top of the floating gate (FG) 110. The mask allows the SiON layer 530 to be selectively etched from the top of the NVM devices. The SiON layer 530 is left on top of the CMOS devices. The absence of SiON layer 530 over the top of the floating gate (FG) 510 breaks the charge leakage path. Electrons on the floating gate (FG) 510 therefore have a much slower decay rate by tunneling in oxide instead of going through a relatively leaky SiON layer 530 that is connected to the substrate.
A second approach has been to increase the thickness of the TEOS layer 520. This increases the tunneling distance from the floating gate (FG) 510 to the SiON layer 530. This causes the electrons to take a longer time to arrive at the relatively leaky SiON layer 530.
A third approach has been to modulate the density of the defects/traps in the TEOS layer 520 in order to make the TEOS layer 520 highly non-conductive. The fewer defects/traps there are in the TEOS layer 520, the less conductivity there is in the TEOS layer 520. Electrons that arrive at the TEOS layer 520 will have difficulty in traveling to other locations. The electrons that collect in the TEOS layer 520 will deter further leakage of electrons from the floating gate (FG) 510.
CMOS compatible NVM performance is not as good as other types of NVM technology (e.g., stacked gate NVM, split gate NVM, SONOS (silicon-oxide-nitride-oxide-silicon) NVM). CMOS compatible NVM performance has slow speed, low density and limited endurance. But it has one major advantage. It has low cost because its fabrication process is compatible with CMOS processes. CMOS compatible NVM technology is advantageous in some applications where limited speed, density and endurance NVM technology is needed but the cost would be too high if mainstream NVM technology were employed. Therefore, the low cost feature is critical to CMOS compatible NVM technology.
The three approaches mentioned above for improving CMOS compatible NVM retention performance have significant drawbacks. The first approach requires the addition of a mask and etch step to the standard CMOS process. This increases the cost. More importantly, when etching the SiON layer 530 from the top of the floating gate (FG) 510, limited etch selectivity between the SiON layer 530 and the TEOS layer 520 always leads to some over-etch of the TEOS layer 520. A thinner TEOS layer 520 will lead to an increased level of electron discharge from the floating gate (FG) 510. In addition, etching away the SiON layer 530 will expose the floating gate (FG) 510 and the TEOS layer 520 to backend plasma damage. This will lead to a degradation of the NVM device retention.
The second approach requires an increase in the thickness of the TEOS layer 520. In order to get a satisfactory retention performance the TEOS layer 520 needs to have at least a double thickness. The creation of a thicker TEOS layer 520 alters the CMOS process and significantly alters the device parameters. After this step the NVM device is no longer CMOS compatible.
The third approach results in plasma induced damage. The CMOS process requires that the SiON layer 530 be leaky so that charges from the plasma process have a leakage path.
Furthermore, it is known that the presence of a sharp corner at the edge of the floating gate increases the electron tunneling current from the floating gate. This increase in electron tunneling current from the floating gate further degrades the retention reliability of the memory cell.
Consider, for example, the tunneling electron microscope (TEM) photograph 600 shown in FIG. 6. Photograph 600 illustrates a cross sectional view of a corner of a prior art floating gate (FG) showing that the coverage of the oxide layer over the floating gate is much thinner at the corner and edge of the floating gate (than over the top of the floating gate). As shown in the photograph 600, the thickness of the coverage of the oxide layer over the top of the floating gate (indicated with double arrows) is approximately two hundred Angstroms (200 Å). As also shown in the photograph 600, the thickness of the oxide layer at the corner and edge of the floating gate (FG) (also indicated with double arrows) is approximately thirty one Angstroms (31 Å).
The difference in thickness is due to the process limitations of the oxide deposition process. The thinness of the oxide layer at the corner of the floating gate contributes to the loss of electrons from the floating gate and increases the backend leakage current of electrons from the floating gate. The thinness of the oxide layer at the corner of the floating gate significantly degrades the retention liability of the EEPROM memory cell.
One prior art approach to solving this problem is to etch the floating gate at a tilted angle. Another prior art approach is the deposit extra amounts of oxide to make the oxide layer thicker and both the center and the edge of the floating gate. These prior art approaches can reduce the backend leakage current of the electrons from the floating gate and improve retention reliability. However, these approaches require changes to the core CMOS process and/or add extra processing steps. This increases the cost and complexity of manufacturing the CMOS compatible EEPROM memory cell.
The prior art approaches are deficient in that they can not increase the oxide thickness at the corner of the floating gate without changing the core CMOS process and/or adding extra cost and processing steps. The optical proximity correction can be applied to change the two dimensional shape of the floating gate (as seen from a top down view) to round the corner of the floating gate. However, this does not change the vertical shape of the floating gate (as seen in a cross sectional view) and does not solve the problem of the thinness of the oxide layer at the edge of the floating gate.
Therefore, there is a need in the art for a system and a method that can (1) alter the cross sectional shape of the floating gate to enable the deposition of a thicker oxide layer at the edge of the floating gate, and (2) thereby reduce charge leakage from the floating gate and increase retention reliability of the memory cell, and (3) not increase the cost and complexity of manufacturing the memory cell. There is a need in the art for a system and a method that can increase the retention reliability of the floating gate of the CMOS compatible memory cell without increasing the manufacturing cost and without changing the core CMOS manufacturing process of the memory cell.
The present invention provides a system and method for altering the cross sectional shape of the floating gate to enable the deposition of a thicker oxide layer at the edge of the floating gate. In one advantageous embodiment of the present invention, a mask structure is prepared that has portions that form a plurality of apertures near the edges of the mask structure. The size of the apertures are intentionally selected to be less than a resolution limitation of a Photo Exposure System.
The mask structure of the invention is placed over a photo resist material. The photo resist material is exposed to a light source of the Photo Exposure System through the mask structure. Only zero order diffraction light can pass through the apertures because the size of the apertures is less than the resolution limitation. The zero order diffraction light imparts enough accumulated energy to partially change the exposed portions of the photo resist material.
A subsequent develop process removes portions of the photo resist material that were exposed to the zero order diffraction light through the apertures to form a sloped surface from the top to the edge of the photo resist material. The resulting sloped surface photo resist pattern is subsequently transferred to a floating gate of a nonvolatile memory cell in a polysilicon etch process.
The sloped edge of the floating gate is then covered with a dielectric layer during a manufacturing process of a CMOS compatible nonvolatile memory cell. The thickness of the dielectric layer over the sloped edge of the floating gate reduces the backend leakage current of electrons from the floating gate and thus improves the retention reliability of the nonvolatile memory cell.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.